Exploring the Impact of Split Locks on Modern x86 Architectures
By Chester Lam

AI Summary
Split locks are atomic operations that span across cache line boundaries, causing significant performance issues on modern CPUs. These operations are crucial for multithreaded code, allowing threads to perform actions without interference. However, when a split lock occurs, it forces the CPU to use a 'bus lock', which can drastically slow down performance by disrupting other cores. AMD and Intel have developed methods to trap split locks, enabling the kernel to detect and mitigate these effects. Testing with various CPUs, including Intel's Arrow Lake and AMD's Zen architectures, reveals that split locks can severely impact memory access performance, particularly beyond L2 cache.
In practical tests, split locks significantly increased core-to-core latency, with results varying across different CPU architectures. For instance, Intel's Arrow Lake showed severe latency issues, especially affecting L2 misses, while AMD's Zen 5 also suffered from high latency under split lock conditions. Interestingly, older architectures like AMD's Piledriver and Intel's Skylake handled split locks better, with less performance degradation.
Linux systems attempt to mitigate split lock effects by introducing delays, which can help maintain performance consistency in multi-user environments. However, this approach may be overly cautious for consumer systems, where split locks are less likely to cause noticeable issues. The Linux default setting aims to prevent 'noisy neighbor' effects but can lead to unnecessary performance problems in some cases.
Overall, while split locks do not completely halt other cores, they introduce significant performance penalties, especially when memory accesses miss certain cache levels. The impact varies depending on the hardware and the frequency of cache misses. Developers should aim to avoid split locks due to their poor performance and potential to affect other applications. Hardware manufacturers also have room to optimize split lock handling to reduce these negative effects.
Key Concepts
Split locks are atomic operations that access memory across cache line boundaries, causing a CPU to lock the bus to maintain atomicity, which can slow down performance.
Cache coherency is a protocol that ensures consistency of data stored in local caches of a shared resource, preventing data corruption in multiprocessor systems.
Category
TechnologyMore on Discover
Summarized by Mente
Save any article, video, or tweet. AI summarizes it, finds connections, and creates your to-do list.
Start free, no credit card